1. Field of the Invention
The present invention relates to synchronous RAMs and particularly to the timing of the enable signal provided to a dynamic sense amplifier in a synchronous RAM.
2. State of the Art
Synchronous (i.e. clocked) memory systems, and particularly synchronous random access memories are designed for speed and low power consumption. Specifically, whereas non-clocked memory systems apply input address signals at various times to the memory inputs within a given time interval resulting in relatively slow response times and delays, synchronous memory systems clock input address signals to the memory inputs with minimal delays.
Another manner in which synchronous RAMs are optimized for speed and power consumption is the manner in which the memory array is organized. For instance, a basic memory array is arranged into rows and columns of memory cells. The memory cells are accessible by selecting the intersection of a word (i.e. row) line and column line of a memory cell within the array. The problem with this type of design is that in a N row x M column array each word line is coupled to M cells and particularly to the gate of an MOS device in each cell. The combination of the gate capacitance of these MOS devices and the parasitic resistance of long word lines results in a significant RC constant associated with each word line, resulting in slow signal propagation on the word line, and hence overall slow memory system operation.
FIG. 1A shows one manner in which this capacitive loading effect is avoided in the memory array of a synchronous RAM. In order to reduce the number of capacitive elements coupled to the word line of a memory array, the array is divided into sections of columns (e.g. section 0, section 1 through section 7) and instead of using a word line to access each of the cells in a given row, a group of local word lines (LWL) in each of the sections are accessed by a global word line (GWL). A sub-word line (SWL) selects the particular LWL in the section. For example, to access a cell in section 0 on one of the LWL lines selectable by GWL(0), GWL(0), one of the SWLOs, and a column needs to be selected. FIG. 1B shows the logic used to access one of the LWLs using SWL and GWL accessing signals which includes one or more logic gates (e.g. AND gates in FIG. 1B). When GWL(0) and one of the SW0 lines are selected, one of the LWLs will also be selected. The selected column then determines which cell is accessed. Referring to FIGS. 1A and 1B, in the case of the N row x M column array in which the columns have been divided into eight sections, the loading on the global word line has been reduced from M cells to 32 AND gates. This represents a significant reduction in capacitive loading of the word line thereby reducing delays within the circuit. It should be noted that FIGS. 1A and 1B do not show actual memory cells or bit lines from memory cells and instead primarily illustrates the access circuitry and signals used to access the memory cells in the array. However, it is well understood in the industry that each memory cell includes a bit line or lines which couple to the sense amplifier in order to read the data from each cell once it has been accessed.
Still another manner in which to optimize power and speed performance in a synchronous RAM is to use dynamic sense amplifiers which are fast and do not dissipate any quiescent (i.e. idle) power. FIG. 2 shows an example of a typical fully differential dynamic sense amplifier having two inputs coupled to the BIT and BIT/ lines from a cell in the array. A sense amplifier enable signal (ENABLE) which is synchronized with a system clock edge, is applied to the sense amplifier causing it to latch to its output ports OUT and OUT/ whatever logic level is present on the BIT and BIT/ inputs of the amplifier at the time the enable signal is applied. Any changes to the BIT and BIT/ lines after the application of the latch enable signal has no affect on the output of the dynamic sense amplifier. As a result, applying the enable signal prior to when the BIT and BIT/ signals are ready would produce erroneous outputs. Alternatively, delaying the enable signal to ensure that the BIT and BIT/ inputs are ready results in increased read access times.
The problem with using dynamic sense amplifiers, global word lines and sub-word lines within a synchronous RAM design is that the GWL and SWL can introduce variable access times to the cells due to variable signal propagation delays on these lines when accessing the array and as a result, the optimal time to apply the enable signal to the dynamic sense amplifier can also vary. Consequently, in current synchronous RAM designs, the enable signal, which is currently synchronized to the system clock edge, is delayed to allow for a worst case access time in order to ensure that the BIT and BIT/ lines are ready to be read. In this way, any signal propagation delays due to process and temperature variations within a given tolerance window are accounted for. However, this is a less than optimal design since the BIT and BIT/ signals may be ready prior to the delayed sense amplifier enable signal being applied depending on the particular device's operating temperature and its previous processing conditions.
What is needed is a synchronous RAM design using a dynamic sense amplifier in which the enable signal is provided to the sense amplifier at the optimal time for reading the bit lines of the array.